1. Field of the Invention
The present invention relates to programmable logic devices and in particular to an in-system programming scheme for those devices.
2. Description of the Related Art
Programmable logic devices (PLDS) typically make use of one or more non-volatile memory cell (e.g. EPROM, EEPROM, Flash EPROM, or Flash EEPROM) arrays which programmably create data paths and logic functions within the device that are specific to the user's design. Typically, these arrays are erasable, thereby allowing the desired functionality of the PLD to be re-programmed many times.
Various types of program, erase, and verify operations allow the user to program and re-program the PLD. For PLDs that are programmed out-of-system in a programming socket, much of the burden for programming, erasing and verifying the contents of the memory arrays is placed on the software controlling the programmer. Additionally, out-of-system programmers typically have parallel access to the address and data pins of the chip, thereby allowing the programming software to cycle quickly through the necessary address and data packets needed to program the device, which contributes to the efficiency of the programming operation.
However, the industry is increasingly using PLDs that can be programmed and erased in-system, that is, while these devices are soldered into place on the circuit board in which the devices will be used. Because the programming software is much more restricted in its access to the in-system PLD, more of the burden for the program, erase, and verify procedures is placed on the chip itself.
As is well known to those in the art, the term In-System Programming (hereinafter ISP) refers to the entire process of programming a device in-system, and, therefore, encompasses the actions of erasing and verifying the design in the device in addition to the specific action of memory cell programming. For ISP processes, the programming software is conventionally limited to serial access to the device through a small number of dedicated pins (typically 4 or 5). This configuration immediately makes the program, erase, and verify operations less efficient because communication with the chip is limited to a single serial port through which all address and data information, as well as the necessary ISP instructions, must enter the device.
Additionally, the high-voltage power supply bus for programming of the device is not available. Thus, internal charge-pumps are required on-chip to generate the necessary voltage levels from conventional internal standard Vcc levels (4.5-5.5V). However, the on-chip charge-pumps cannot provide the quick, strong drive of an external supply. Therefore, programming and erasing operations for ISP devices can be significantly less efficient than operations for out-of-system devices.
Typically, an ISP device contains a number of different instruction and data shift registers which are accessed through the same serial port. These registers are used to hold the instruction code or the address and data values which might ordinarily be driven at the pins of the device in a parallel, out-of-system programming process. In this ISP process, the controlling software includes ISP instructions which control access to the data registers and determine which ISP operation is currently active.
In programming data to the location(s) addressed by a single address, a typical ISP algorithm may require that a LOAD instruction be entered serially into the ISP device, followed by the serial entry of an address/data packet. Then, the LOAD instruction is terminated and the actual PROGRAM instruction is shifted into the registers, thereby initiating the programming cycle for the current address/data. After the programming cycle, an additional VERIFY instruction may be required to verify that the intended data was successfully programmed at the given address.
Because there is only one serial port available for entering ISP instructions as well as address/data packets, a typical ISP device requires multiple switches between instructions and data for each address during programming, thereby decreasing the device's efficiency. Therefore, a need arises for a method of performing efficient in-system programming, erasing, and design verification of PLDS.